NVC - VHDL Compiler and Simulator

Language Support

NVC supports almost all of IEEE 1076-1993 and 1076-2002. Please report any missing or incorrectly implemented features.

VHDL-2008

IEEE 1076-2008 was a major update to the VHDL standard. NVC supports many of the new features, please consult the table below.

FeatureStatus
Package generics 1.6
Subprogram generics 1.7
Generic types 1.7
PSL integrated into VHDL
New fixed and floating point arithmetic packages 1.7
/* */ block comments 1.6
New standard functions minimum, maximum, to_string, etc. 1.6
Function rising_edge is defined for boolean 1.7
Arrays and records may contain unconstrained elements 1.7
New boolean_vector, integer_vector, etc. types 1.6
"Matching" case statement case? 1.7
force and release for signals 1.7
'INSTANCE_NAME etc. extended for package and subprogram instantiation 1.11
New standard environment package 1.4
New 'SUBTYPE and 'ELEMENT attributes 1.7
New condition operator ?? 1.6
Enhanced bit string literals 1.6
External names 1.11
Array slices in aggregates 1.7
Conditional and selected sequential statements 1.10
Extensions to generate statement 1.8
all in sensitivity list 1.6
Context declarations 1.4
New and enhanced IEEE standard packages 1.6

VHDL-2019

IEEE 1076-2019 was another major update to the VHDL standard. NVC has experimental support for some of the new features, please consult the table below.

LCSFeatureStatus
LCS2016-001 Partially connected vectors on port map 1.11
LCS2016-002 Allow access to protected type parameters on function interfaces 1.11
LCS2016-004 Allow PT methods with AT and FT parameters 1.11
LCS2016-006a File IO / TextIO updates 1.9
LCS2016-006c Directory API 1.11
LCS2016-006e Environment API 1.10
LCS2016-006f Expose standard conditional analysis identifiers 1.9
LCS2016-007 Sequential declaration regions 1.11
LCS2016-011 Date/time functions 1.10
LCS2016-012 'IMAGE and TO_STRING for composite types 1.11
LCS2016-014 Composites of protected types
LCS2016-014a Pointers to composites of protected types 1.10
LCS2016_015 Standard functions to report calling path 1.9
LCS2016_015a Standard functions to report current file name 1.9
LCS2016-016 Anonymous types
LCS2016-018 Attributes for enumerated types 1.11
LCS2016-018a New attributes - 'INDEX 1.10
LCS2016-018d New attributes - 'DESIGNATED_TYPE 1.10
LCS2016-019 Inferring constraints from initial values for signals and variables 1.10
LCS2016-023 Relax library requirement on configurations 1.11
LCS2016-026c Long integers 1.10
LCS2016_030 Garbage collection 1.7
LCS2016-032 PATH_NAME and INSTANCE_NAME and protected types 1.11
LCS2016-033 Composition with protected types 1.11
LCS2016-034 Protected types with generic clause
LCS2016-036a Allow for conditional expressions in a declaration (baseline) 1.10
LCS2016-041 Record introspection/type reflection 1.11
LCS2016-043 Attributes for PSL
LCS2016-045a Interface - defines new mode view construct for composite interface objects 1.11
LCS2016-045c Interface - 'CONVERSE for a mode view 1.10
LCS2016-047 Protected type: shared variables on entity interface 1.10
LCS2016-049 Map generics on subprogram call 1.14
LCS2016-050 API for assert 1.11
LCS2016-055a Syntax regularisation - component declarations 1.9
LCS2016-059 Array type generics 1.14
LCS2016-059a Allow ordering on any scalar array 1.10
LCS2016_061 Conditional compilation 1.4
LCS2016_071a Optional trailing semicolon 1.9
LCS2016_072b Function knows vector size 1.10
LCS2016_075 Closely related record types 1.11
LCS2016_082 Empty record 1.9
LCS2016_086 All interface lists can be ordered 1.9
LCS2016_094a Conditional return statement 1.10
LCS2016_099 Extended ranges
LCS2016_I03 Signatures required in association lists 1.14
LCS2016_I13 Precedence of unary operators 1.14

Property Specification Language (PSL)

NVC supports the "simple subset" of IEEE 1850-2010. PSL directives may be written directly in VHDL if using VHDL-2008 or later, or embedded in comments. Not all features are currently supported, please consult the table below.

LRM SectionFeatureStatus
5 Boolean Layer
5.1 Boolean expressions 1.15
5.1.1 Bit expressions 1.15
5.1.2 Boolean expressions 1.15
5.1.3 Bit Vector expressions 1.15
5.1.4 Numeric expressions 1.15
5.1.5 String expressions 1.15
5.2 Expression forms 1.15
5.2.1 HDL expressions 1.15
5.2.2 PSL expressions
5.2.3 Built-in functions 1.15
5.2.3.1 prev() 1.16
5.2.3.2 next()
5.2.3.3 stable() 1.16
5.2.3.4 rose() 1.16
5.2.3.5 fell() 1.16
5.2.3.6 ended()
5.2.3.7 isunknown() 1.15
5.2.3.8 countones() 1.15
5.2.3.9 nondet()
5.2.3.10 nondet_vector()
5.2.3.11 onehot(), onehot0() 1.15
5.2.4 Union expressions 1.16
5.3 Clock expressions
5.4 Default clock declaration 1.15
6 Temporal Layer
6.1 Sequential Expressions 1.15
6.1.1 Sequential Extended Regular Expressions (SEREs) 1.15
6.1.1.1 Simple SEREs 1.15
6.1.1.1.1 SERE concatenation (;) 1.15
6.1.1.1.2 SERE fusion (:) 1.15
6.1.1.2 Compound SEREs
6.1.1.2.1 SERE or (|)
6.1.1.2.2 SERE non-length-matching and (&)
6.1.1.2.3 SERE length-matching and (&&) 1.15
6.1.1.2.4 SERE within
6.1.1.2.5 Parameterized SERE
6.1.2 Sequences 1.15
6.1.2.1 SERE consecutive repetition ([* ]) 1.15
6.1.2.2 SERE non-consecutive repetition ([= ]) 1.15
6.1.2.3 SERE goto repetition ([-> ]) 1.15
6.1.2.4 Braced SERE 1.15
6.1.2.5 Clocked SERE (@)
6.2 Properties 1.15
6.2.1 FL Properties 1.15
6.2.1.1 Sequential FL Properties 1.15
6.2.1.2 Clocked FL Properties
6.2.1.3 Simple FL Properties 1.15
6.2.1.3.1 always 1.15
6.2.1.3.2 never 1.15
6.2.1.3.3 eventually! 1.15
6.2.1.3.4 next 1.15
6.2.1.4 Extended next FL Properties
6.2.1.4.1 next_a
6.2.1.4.2 next_e
6.2.1.4.3 next_event
6.2.1.4.4 next_event_a
6.2.1.4.5 next_event_e
6.2.1.5 Compound FL Properties 1.15
6.2.1.5.1 abort, async_abort and sync_abort 1.15
6.2.1.5.2 before 1.15
6.2.1.5.3 until 1.15
6.2.1.6 Sequence-based FL Properties 1.15
6.2.1.6.1 Suffix implication 1.15
6.2.1.7 Logical FL Properties
6.2.1.7.1 Parametrized property
6.2.1.7.2 Logical implication
6.2.1.7.3 Logical iff
6.2.1.7.4 Logical and
6.2.1.7.5 Logical or
6.2.1.7.6 Logical not
6.2.1.8 LTL operators
6.2.2 Optional Branching Extension (OBE) properties N/A
6.2.3 Replicated properties
6.3 Local variables
6.4 Procedural blocks
6.5 Property and sequence declarations
6.5.1 Parameters
6.5.1.1 PSL formal parameter type classes
6.5.1.2 HDL formal parameter type classes
6.5.2 Declarations
6.5.2.1 Sequence Declarations
6.5.2.2 Property Declaration
6.5.3 Instantiation
6.5.3.1 Sequence instantiation
6.5.3.2 Property instantiation
7 Verification Layer
7.1 Verification directives 1.15
7.1.1 assert 1.15
7.1.2 assume
7.1.3 restrict
7.1.4 restrict!
7.1.5 cover 1.15
7.1.6 fairness and strong_fairness
7.2 Verification units
7.2.1 Verification unit binding
7.2.2 Verification unit instantiation
7.2.3 Verification unit inheritance
7.2.4 Overriding assignments
7.2.4.1 Simple case
7.2.4.2 Multiple unrelated vunits
7.2.4.3 Multiple overrides to the same signal
8 Modeling layer
8.1 Integer ranges
8.2 Structures
8 Scope and visibility rules
9.1 Immediate scope
9.2 Extended scope
9.3 Direct and indirect name references