NVC - VHDL Compiler and Simulator

Language Support

NVC supports almost all of IEEE 1076-1993 and 1076-2002. Please report any missing or incorrectly implemented features.

VHDL-2008

IEEE 1076-2008 was a major update to the VHDL standard. NVC has experimental support for some of the new features, please consult the table below.

FeatureStatus
Package generics 1.6
Subprogram generics 1.7
Generic types 1.7
PSL integrated into VHDL
New fixed and floating point arithmetic packages 1.7
/* */ block comments 1.6
New standard functions minimum, maximum, to_string, etc. 1.6
Function rising_edge is defined for boolean 1.7
Arrays and records may contain unconstrained elements 1.7
New boolean_vector, integer_vector, etc. types 1.6
"Matching" case statement case? 1.7
force and release for signals 1.7
'INSTANCE_NAME etc. extended for package and subprogram instantiation
New standard environment package 1.4
New 'SUBTYPE and 'ELEMENT attributes 1.7
New condition operator ?? 1.6
Enhanced bit string literals 1.6
External names 1.7
Array slices in aggregates 1.7
Conditional and selected sequential statements 1.6
Extensions to generate statement
all in sensitivity list 1.6
Context declarations 1.4
New and enhanced IEEE standard packages 1.6

VHDL-2019

IEEE 1076-2019 was another major update to the VHDL standard. NVC has experimental support for some of the new features, please consult the table below.

LCSFeatureStatus
LCS2016_061 Conditional compilation 1.4
LCS2016_030 Garbage collection 1.7