NVC - VHDL Compiler and Simulator

NVC(1) General Commands Manual NVC(1)

nvcVHDL Compiler and Simulator

nvc -a file ...

nvc -e unit

nvc -r unit

nvc is an implementation of the VHDL language as defined by IEEE standard 1076-1993 and later revisions.

Simulating a design typically involves three steps: analysing one or more source files into the work library; elaborating a top-level design unit; and finally running the elaborated design.

nvc accepts three kinds of options: global options; commands; and options specific to the command. Global options must be placed before the command and specific options must be placed after the command.

file ...
Analyse one or more files into the work library. Reads from standard input if file is ‘-’.
Elaborate a previously analysed top level design unit.
Execute a previously elaborated top level design unit.
file ...
Process code coverage data from file and generate coverage report.
Export collected coverage information for a previously executed top level design unit to an external format such as Cobertura XML.
Print out a pseudo-VHDL representation of an analysed unit. This is usually only useful for debugging the compiler.
Initialise the working library directory. This is not normally necessary as the library will be automatically created when using other commands such as -a.
Execute scripts to compile common verification frameworks and FPGA vendor libraries.
Print all analysed and elaborated units in the work library.
unit ...
Generate a makefile for already analysed units.
file ...
Check input files for syntax errors only.

Commands can be chained together arbitrarily and the top-level unit name need only be specified once. For example to analyse a file ‘source.vhd’ and then elaborate and run a top-level entity ‘tb’:

$ nvc -a source.vhd -e tb -r

Or to elaborate again with coverage collection enabled, run the simulation, and export the data to the Cobertura format:

$ nvc -e --cover tb -r --cover-export --format=cobertura -o out.xml

Note how the unit argument for the -r and --cover-export commands is taken from the earlier -e command.

, --help
Display usage summary.
Set the maximum size in bytes of the simulation heap. This area of memory is used for temporary allocations during process execution and dynamic allocations by the VHDL ‘new’ operator. The size parameter takes an optional k, m, or g suffix to indicate kilobytes, megabytes, and gigabytes respectively. The default size is 16 megabytes.
Do not check the timestamps of source files when the corresponding design unit is loaded from a library.
Add path to the list of directories to search for libraries. See the LIBRARIES section below for details.
Set the maximum amount of memory in bytes used for the internal representations of design units. The default is 16 megabytes but this may be insufficient when elaborating a large design. The size parameter takes an optional k, m, or g suffix to indicate kilobytes, megabytes, and gigabytes respectively. For example -M64m for 64 megabytes.
Specify exactly the location of the logical library name. Libraries mapped in this way will not use the normal search path.
Select the format used for printing error and informational messages. The default full message format is designed for readability whereas the compact messages can be easily parsed by tools.
Select the VHDL standard revision to use. VHDL standard revisions are commonly referred to by the year they were published. For example IEEE 1076-1993 is known as VHDL-93. Specify either the full year such as 1993 or just the last two digits such as 93. The accepted revisions are 1993, 2000, 2002, 2008, 2019. Note there is very limited supported VHDL-2019 at present and VHDL-87 is not supported. The default standard revision is VHDL-2008.
Print error messages with the given severity or higher to ‘stderr’ instead of ‘stdout’. The default is to print all messages to ‘stderr’. Valid levels are note, warning, error, and failure.
, --version
Display version and copyright information.
=name, --work=name:path
Use name as the work library. The second variant explicitly specifies the location of the library. See the LIBRARIES section below for details.

Allow compilation of the ‘STANDARD’ package. Not useful in any other circumstances.
Stop after reporting num errors. The default is 20. Zero allows unlimited errors.
list, --files=list
Read the list of source files to analyse from list which is a text file containing one file name per line. If list is ‘-’ then reads from the standard input instead. Comments starting with ‘#’ are ignored. Alternatively this argument may be passed as @list for compatibility with other tools.
Enable parsing of PSL directives in comments.
Disable certain pedantic LRM conformance checks or rules that were relaxed by later standards. See the RELAXED RULES section below for details.
name=value, --define=name=value
Define a conditional analysis identifier (VHDL-2019). Option can be used multiple times to define multiple identifiers.

Enable code coverage reporting (see the CODE COVERAGE section below).
Specify design part where code coverage is collected by sfile coverage specification file (see the CODE COVERAGE section below).
Write generated LLVM IR to the work library directory before and after optimisation.
Print generated intermediate code. This is only useful for debugging the compiler.
Override generic name with value. Integers, enumeration literals, and string literals are supported. Generics in internal instances can be overridden by giving the full dotted path to the generic. For example -gI=5, -gINIT='1', and -gUUT.STR="hello".
, --jit
Normally nvc compiles all code ahead-of-time during elaboration. The --jit option defers native code generation until run-time where each function will be compiled separately on a background thread once it has been has been executed often enough in the interpreter to be deemed worthwhile. This dramatically reduces elaboration time at the cost of increased memory and CPU usage while the simulation is executing. This option is beneficial for short-running simulations where the performance gain from ahead-of-time compilation is not so significant.
Do not collapse ports into a single signal. Normally if a signal at one level in the hierarchy is directly connected to another signal in a lower level via a port map, the signals are “collapsed” and only the signal in the upper level is preserved. The --no-collapse option disables this optimisation and preserves both signals. This improves debuggability at the cost of some performance.
Do not save the elaborated design and other generated files to the working library. This is only really useful in combination with the -r option. For example:
$ nvc -e --no-save tb -r
, -01, -02, -O3
Set LLVM optimisation level. Default is -O2.
, --verbose
Prints resource usage information after each elaboration step.

Include memories and nested arrays in the waveform data. This is disabled by default as it can have significant performance, memory, and disk space overhead.
Terminate the simulation after an assertion failures of severity greater than or equal to level. Valid levels are note, warning, error, and failure. The default is failure.

This option also overrides the minimum severity level which causes the program to return a non-zero status code. The default is error which allows assertion violations to be detected easily.

Generate waveform data in format fmt. Currently supported formats are: fst and vcd. The FST format is native to gtkwave(1). FST is preferred over VCD due its smaller size and better performance. VCD is a very widely used format but has limited ability to represent VHDL types and the performance is poor: select this only if you must use the output with a tool that does not support FST. The default format is FST if this option is not provided. Note that GtkWave 3.3.79 or later is required to view the FST output.
, --gtkw[=file]
Write a gtkwave(1) save file containing every signal in the design hierarchy in declaration order with separators for each scope. This only makes sense in combination with the --wave option.
Enable or disable warning messages from the standard IEEE packages. The default is warnings enabled.
glob, --exclude=glob
Signals that match glob are included in or excluded from the waveform dump. See section SELECTING SIGNALS for details on how to select particular signals. These options can be given multiple times.
Loads a VHPI plugin from the shared library plugin. See section VHPI for details on the VHPI implementation.
Run processes in random order. The VHDL standard does not specify the execution order of processes and different simulators may exhibit subtly different orderings. The --shuffle option can help to find and debug code that inadvertently depends on a particular process execution order. This option should only be used during debug as it incurs a significant performance overhead as well as introducing potentially non-deterministic behaviour.
Print a summary of the time taken and memory used at the end of the run.
Stop after N delta cycles. This can be used to detect zero-time loops in your model. The default is 10000 if not specified. Setting this to zero disables the delta cycle limit.
Stop the simulation after the given time has elapsed. Format of T is an integer followed by a time unit in lower case. For example 5ns or 20ms.
Trace simulation events. This is usually only useful for debugging the simulator.
Report any VHPI errors as diagnostic messages on the console. Normally these are only returned through the () function.
Trace VHPI calls and events. This can be useful for debugging VHPI plugins.
, --wave[=file]
Write waveform data to file. The file name is optional and if not specified will default to the name of the top-level unit with the appropriate extension for the waveform format. The waveform format can be specified with the --format option. By default all signals in the design will be dumped: see the SELECTING SIGNALS section below for how to control this.

Merge multiple file code coverage databases into output code coverage database.
Generate HTML code coverage report to dir directory.
Apply commands in efile exclude file when generating code coverage report.
When set, NVC does not place code coverage details specified by <options> to code coverage report. options is comma separated list of the following values:
Does not include covered items.
Does not include uncovered items.
Does not include excluded items.
NVC displays maximum limit items of single type (covered, uncovered, excluded) in a single hierarchy in the code coverage report. Default value of limit is 5000.
, --verbose
Prints detailed hierarchy coverage when generating code coverage report.

Output file format. Currently the only valid value is ‘cobertura’ which is the Cobertura XML format widely supported by CI systems.
, --output=file
Write output to file. If this option is not specified the standard output stream is used.
Strip path or the current working directory from the front of any absolute path names in the output.

Generate rules that only contain dependencies without actions. These can be useful for inclusion in a hand written makefile.
The generated makefile will work with any POSIX compliant make. Otherwise the output may use extensions specific to GNU make.

Compile libraries into directory dir instead of the default $HOME/.nvc/lib.

A library is a directory containing analysed design units and other files generated by nvc. The default library is called "work" and is placed in a directory also called work. Note that VHDL also has a concept of the "work library" where the current library can be referred to by the alias work. This confusing behaviour is an unfortunate hangover from the proprietary tools the author used prior to writing nvc.

The name and physical location of the work library is controlled by the --work global option. In the simple case of --work=name the library name is ‘name’ and the physical location is a directory name relative to the current working directory. The physical location can be specified explicitly using --work=name:path where path is the directory name. On Windows the ; character can be used instead of : as a separator.

The following examples should make this behaviour clear:

$ nvc --work=mylib ...

The work library is named ‘mylib’ and is mapped to a directory with the same name in the current working directory.

$ nvc --work=mylib:somedir ...

The work library is named ‘mylib’ and is mapped to a directory somedir in the current working directory.

$ nvc --work=mylib:/foo/bar ...

The work library is named ‘mylib’ and is mapped to the absolute path /foo/bar.

Concurrent access to a single library by multiple processes is completely safe and protected by a lock in the filesystem using flock(2) that allows multiple concurrent readers but only a single writer.

nvc can collect code coverage data while the simulation is executing. The following coverage types are supported:

  • - For each statement, NVC creates coverage bin. When statement is executed, it is covered.
  • - For each point where code diverges (if/else, case, when/else, with/select statements), NVC creates coverage bin. If branch can be evaluated to both true and false, NVC creates two coverage bins for such branch (one for each of true/false)
  • - Each signal of type derived from ‘std_logic’ (including nested arrays) creates two coverage bins (to track 0 -> 1 and 1 -> 0 transitions).
  • - NVC creates multiple coverage bins for combinations of input operands of the following logical operators: ‘and’,‘nand’,‘or’,‘nor’,‘xor’,‘xnor’,such that propagation of operand values causes the expression result to change its value. Further, NVC creates two coverage bins for evaluating expression result to ‘True’ and ‘False’ for the following operators: ‘=’,‘/=’,‘>’,‘<’,‘<=’,‘>=’,‘not’.NVC collects expression coverage also on overloaded logic operators from ‘ieee.std_logic_1164’ library. It tracks combinations of input values to logic operators for ‘std_logic’ operand type. NVC does not collect expression coverage for VHDL 2008 overloaded operands for ‘std_logic_vector’ type.
  • - NVC tracks if states of Finite State Machines (FSMs) are visited. NVC creates a coverage bin for each state of an FSM. NVC considers internal signals of all user-defined enum types as FSMs. NVC does not consider port signals or variables as an FSM.
  • - NVC creates a coverage bin for each PSL ‘cover’ directive.

Collection for each coverage type can be enabled separately at elaboration time:

$ nvc -e --cover=statement,branch,toggle,expression <top>

If no coverage type is specified as an argument of --cover, all coverage types are collected. After simulation is executed, NVC dumps coverage data into coverage database file (*.covdb). To merge coverage databases from multiple simulations, and generate hierarchy coverage report in HTML format, run:

$ nvc -c --merge=merged.covdb --report=<path_to_folder_for_html_report> \
      first.covdb second.covdb third.covdb ...
When NVC merges multiple coverage databse files, coverage items/bins with equal hierarchical paths in the elaborated design are merged together. If a coverage item/bin is covered in at least one of input coverage databases, it is covered in the merged coverage database. NVC creates union of all coverage items from all input coverage databases in the merged coverage database. This allows merging together coverage from different designs (e.g. where part of the hierarchy is formed by "if-generate" statement).

NVC supports the following additional options to control coverage collection:

  • - When set, NVC also counts toggles U -> 1 as 0 -> 1 and toggles U -> 0 as 1 -> 0 during toggle coverage collection.
  • - When set, NVC also counts toggles from/to Z to either of 0/1 as valid 0 -> 1 or 1 -> 0 transitions.
  • - When set, NVC collects toggle coverage on multidimensional arrays or nested arrays (array of array), disabled by default.
  • - When set, NVC does not collect toggle coverage on arrays whose size is equal to or larger than <size>
  • - When set, NVC detects unreachable coverage bins and automatically excludes them during code coverage report generation. NVC detects following unreachable coverage items:
    • Toggle coverage on instance ports driven by constant value.
  • - When set, NVC by default does not consider signals of usr-define enum types as FSMs. With this option, NVC can be forced to recognize FSMs only via ‘fsm-type’ directive in coverage specification file.

All additional coverage options are passed comma separated to --cover elaboration option, e.g.:

$ nvc -e --cover=all,include-mems,count-from-undefined <top>

Coverage collection on parts of the code can be ignored via a comment pragma, for example:

case (sel) is
  when "00" => ...
  when "01" => ...
  when "10" => ...
  when "11" => ...
  -- coverage off
  when others => report "ERROR" severity failure;
  -- coverage on
end case;

In the example above, statement coverage for the ‘report’ statement and branch coverage for ‘others’ choice will not be collected.

Toggle coverage collection on specific signals can be also disabled:

-- coverage off
signal cnt : std_logic_vector(3 downto 0);
-- coverage on

NVC can collect code coverage only on part of the simulated design. When coverage specification file is passed during elaboration time, NVC collects code coverage only as specified in this file. If the file is ommited, NVC collects code coverage on whole design. The format of commands in the coverage specification file is as follows:

(+|-)block <ENTITY_NAME>
(+|-)hierarchy <HIERARCHY>
(+|-)fsm-type <TYPE>

An example of coverage specification file is following:

# Placing '#' is treated as comment till end of line

# Example how to enable collecting code coverage on a hierarchy:
+hierarchy WORK.TOP.DUT_INST*

# Example how to disable collecting code coverage on a hierarchy:

# Example how to enable collecting code coverage on entity or block:
+block async_fifo

# Example how to disable collecting code coverage on entity or block:
-block clock_gate_model

# Example how to force all signals of enum types named 'T_FSM_STATE'
# to be recognized as FSM
+fsm_type T_FSM_STATE

# Example how to force all signals of enum types with name matching
# 'T_*_FSM' pattern to be recognized as FSM
+fsm_type T_*_FSM

# Example how to force all signals of enum type named 'T_TRANSFER_TYPE'
# not to be recognized as an FSM

In coverage specification file ‘block’ has priority over ‘hierarchy’, disabled hierarchy / block ( ‘-’ ) has priority over enabled hierarchy / block ( ‘+’ ).

NVC can exclude any coverage items when generating code coverage report. When a coverage item is excluded, it is counted as "Covered" in the coverage summary and displayed in a dedicated group in the code coverage report. Format of commands in exclude file is following:

exclude <HIERARCHY> (BIN)

Where ‘<HIERARCHY>’ is the name of coverage item, and ‘BIN’ is one of following bins:

  • - Excludes "Evaluated to: True" bin. Applicable to if/else branch, when/else branch or expression.
  • - Excludes "Evaluated to: False" bin. Applicable to if/else branch, when/else branch or expression.
  • - Excludes "Choice of:" bin. Applicable to case/with branch choices.
  • - Excludes bins for combination of input operands (LHS, RHS) of an expression. Applicable to an expression for which combinations of input operand values is tracked. ‘X’, ‘Y’ shall be 0 or 1. Excludes bin where LHS = ‘X’ and RHS = ‘Y’, see an example exclude file below.
  • - Excludes "Toggle from 0 to 1" bin. Applicable to signal / port toggle coverage.
  • - Excludes "Toggle from 1 to 0" bin. Applicable to signal / port toggle coverage.

If ‘BIN’ is ommited, NVC excludes all bins for given coverage item. An example of exclude file:

# Placing '#' is treated as comment till end of line

# Example how to exclude statement
# For statements BIN shall be ommited
exclude WORK.TOP._P1._S0._S3

# Example how to exclude all coverage items which match wildcard:

# Example how to exclude 4 coverage bins for combinations of input
# operands value (LHS, RHS) of an expression:
exclude WORK.TOP.XOR_GATE._S0._E0 BIN_0_0
exclude WORK.TOP.XOR_GATE._S0._E0 BIN_0_1
exclude WORK.TOP.XOR_GATE._S0._E0 BIN_1_0
exclude WORK.TOP.XOR_GATE._S0._E0 BIN_1_1

# Example which excludes the same items as previous example,
# but excludes all bins by a single command:
exclude WORK.TOP.XOR_GATE._S0._E0

# Example how to exclude branch 'Evaluated to: False' bin:
exclude WORK.TOP._P0._S0._B0 BIN_FALSE

# Example how to exclude toggle bin 'Toggle from 0 to 1' on
# a signal, and all toggle bins on a port of sub-instance:

In coverage specification file and Exclude file ‘<ENTITY_NAME>’ ‘<HIERARCHY>’ and ‘<TYPE>’ are case-insensitive. You can get examples of ‘<HIERARCHY>’ from generated Code coverage report by clicking on a "Get Exclude Command" button.

The --relaxed analysis flag enables “relaxed rules” mode which downgrades the following errors to warnings:

  • Impure function called from pure function.
  • File object declared in pure function.
  • Default expression in object interface declaration is not globally static.
  • Shared variable is not of protected type in VHDL-2000 or later.

Additionally the following languages features from VHDL-2008 and later are enabled in earlier standards:

  • Any visible explicitly declared operator always hides an implicit operator regardless of the region in which it is declared. This is required to analyse code that uses the non-standard Synopsys package.
  • References to generics and array slices are allowed in locally static expressions using the VHDL-2008 rules.
  • Range bounds with ‘universal_integer’ type are not required to be numeric literals or attributes. This option allows ranges such as ‘-1 to 1’ in VHDL-1993 which otherwise must be written ‘integer'(-1) to 1’.

Every signal object in an elaborated design has a unique hierarchical path name. In VHDL this can be accessed using the ‘PATH_NAME’ attribute.

A signal can be referred to using its full path name, for example ‘:top:sub:x’, and ‘:top:other:x’ are two different signals named ‘x’ in the design. The character ‘:’ is a hierarchy separator. The special character ‘*’ is a wildcard that matches zero or more characters and may be used refer to a group of signals. For example ‘:top:*:x’, ‘*:x’, and ‘:top:sub:*’, all select both of the previous signals.

Path names and globs can be used to exclude or explicitly include signals in a waveform dump. For simple cases this can be done using the --include and --exclude arguments. For example --exclude=":top:sub:*" will exclude all matching signals from the waveform dump. Multiple inclusion and exclusion patterns can be provided.

Specifying large numbers of patterns on the command line quickly becomes cumbersome. Instead inclusion and exclusion patterns can be read from a text file. If the top-level unit name is ‘top’ then inclusion patterns should be placed in a file called top.include and exclusion patterns in a file called top.exclude. These files should be in the working directory where the ‘nvc -r’ command is executed. The format is one glob per line, with comments preceded by a ‘#’ character.

When both inclusion and exclusion patterns are present, exclusions have precedence over inclusions. If no inclusion patterns are present then all signals are implicitly included.

nvc supports a subset of VHPI allowing access to signal values and events at runtime. The standard VHPI header file <vhpi_user.h> will be placed in the system include directory as part of the installation process. VHPI plugins should be compiled as shared libraries; for example:

$ cc -shared -fPIC my_plugin.c -o my_plugin.so
$ nvc -r --load my_plugin.so my_tb

The plugin should define a global vhpi_startup_routines which is a NULL-terminated list of functions to call when the plugin is loaded:

void (*vhpi_startup_routines[])() = {

Functions defined in VHPI plugin libraries may be called from VHDL using either the standard VHPI protocol or a simplified protocol similar to ghdl(1)

To use the standard VHPI protocol the VHDL function should be declared with the ‘FOREIGN’ attribute giving the "object library name" and "model name" of the foreign function. For example:

function my_func (x : integer; y : bit_vector; z : std_logic) return integer;
attribute foreign of my_func : function is "VHPI my_lib my_func";

The VHPI plugin should then call () to register the foreign subprogram.

static void my_func_cb(const vhpiCbDataT *cb_data_p) { ... }

vhpiForeignDataT my_func_data = {
   .kind = vhpiFuncF,
   .libraryName = "my_lib",
   .modelName = "my_func",
   .execf = my_func_cb,

To use the simplified protocol the VHDL the ‘FOREIGN’ attribute should be specified with the keyword ‘VHPIDIRECT’ and name of the function symbol exported from the plugin. For example:

function my_func (x : integer; y : bit_vector; z : std_logic) return integer;
attribute foreign of my_func : function is "VHPIDIRECT my_func";

Where ‘my_func’ is a global function defined in the plugin library as follows.

int32_t my_func(int32_t x, const uint8_t *y, int64_t y_len, uint8_t z);

Foreign procedures may be defined similarly:

function my_proc (x : out integer; y : out bit_vector; z : std_logic);
attribute foreign of my_proc : function is "VHPIDIRECT my_proc";

void my_proc(int32_t *x, uint8_t *y, int64_t y_len, uint8_t z);

Note that scalar ‘out’ parameters are passed by pointer.

There is a simple mapping between VHDL and C types.

The smallest C integer type that holds the full range of the VHDL type.
C double regardless of the range of the VHDL type.
Enumerated types
The smallest unsigned integer type that holds the full range of the VHDL type.
Constrained arrays
Pointer to the element type.
Unconstrained arrays
Pointer to the element type followed by one int64_t length argument for each dimension. Note that the bounds and direction are not available and must be passed explicitly as separate arguments if required.
Not yet supported.

Here are several examples for common types:

INTEGER range 1 to 5 int8_t
uint8_t *
uint8_t *, int64_t

Foreign functions must not modify arrays passed as ‘in’ arguments. Additionally foreign subprograms must not retain any pointers passed as arguments after the subprogram returns. Violating these rules will result in unpredictable and hard to debug behaviour.

Controls whether nvc uses ANSI colour escape sequences to print diagnostic messages. The possible values are never, always, and auto which enables colour if stdout is connected to a terminal. The default is auto.

ghdl(1), gtkwave(1)

Written by Nick Gasson ⟨nick@nickg.me.uk⟩

Report bugs to nick@nickg.me.uk or using the GitHub issue tracker at https://github.com/nickg/nvc/issues. Please include enough information to reproduce the problem, ideally with a small VHDL test case.

April 7, 2024 Debian